GoIT Wiki - User contributions [en]

Standard Cell Libraries

2023-09-28T14:12:30Z

Mmlouerat: Created page with "=Free and Open Source Standard Cell Libraries= In this page, LIP6, (Sorbonne Université & CNRS) wishes to present a survey of the existing open-source standard-cell libraries. This study is part of the [https://wiki.goit-project.eu/index.php?title=Main_Page GoIT] project. This page will be regularly updated, since new Open PDK projects are ongoing, such as the [https://github.com/IHP-GmbH/IHP-Open-PDK IHP Open PDK]. == Different formats and views == A library of Stan..."

=Free and Open Source Standard Cell Libraries=

In this page, LIP6, (Sorbonne Université & CNRS) wishes to present a survey of the existing open-source standard-cell libraries.
This study is part of the [https://wiki.goit-project.eu/index.php?title=Main_Page GoIT] project.
This page will be regularly updated, since new Open PDK projects are ongoing, such as the [https://github.com/IHP-GmbH/IHP-Open-PDK IHP Open PDK].

== Different formats and views ==

A library of Standard Cells provides different descriptions (or views) of each cell. These descriptions are based on different formats and languages. To be compliant with a digital design flow, a cell has to provide at least 3 views:

* '''Logical level model'''. IIt is the model of the functional behaviour represented by a boolean logic function. The model uses the VHDL or the Verilog language. The cell's logic function is used for logic synthesis of a digital circuit. The behavioural model is compatible with event driven simulator for functional verification of a digital circuit. The interface of the cell model (input, output) is used by the place and root operation in the circuit design flow (i.e. circuit layout);
* '''Transistor level netlist'''. It is the description of the interconnection of the set of transistors required to generate the logic behavior. It is written in spice format. This model is compatible with transistor-level simulation with ngspice, which may be used for timing characterization of the cell;
* '''Layout description'''. It is written according to the GDSII format. It is used by place and route software tools to create the layout of the digital circuit that will be sent by the designer for fabrication in a foundry.

Depending on the cell use, other descriptions may also be required:

* Schematic representation of the boolean logic function, for circuit schematic capture;
* Layout and design abstract information (Lef, Def), used by place and route software tools;
* Timing information, Liberty file (lib), used by logic synthesizers and static timing analyzers;
* Post-layout transistor spice netlist including parasitics, used by static timing analyzer and performance estimation (power, timing, area) tools.

== Layout Design approaches ==

Different approaches are used to generate the layout of standard cells, which are:

* '''Custom design'''. For each target process, the layout is edited from scratch with the help of a layout editor and a Design Rule Checker (DRC), such as KLayout.

* '''Scalable design'''. The layout is generated for each target process. The designer of the cell provides a procedural description of the layout (Python scripts can be used).

* '''Symbolic approach'''. Symbolic Layout is a way of making the layout of a chip independent of the target technological node. Symbolic layout is created by drawing the polygons in a blank unit called the lambda. Then, the value of the lambda is calculated for the target technology so that the layout fits its particular design rules. The symbolic layout is translated to real layout, according to the lambda value. This approach was first introduced by Mead and Conway. The symbolic layout allows the designer to show a physical view even when the PDK, and its associated Design Rules Manual (DRM), are distributed subject to NDA.

== Existing Open Source Libraries of Standard Cells ==
There are some open source libraries available today. They are listed below, with available download link, depending on the approach they are using for layout generation. They have already inspired a lot of EDA software and circuit designers, not to mention the thousands of VLSI students. As Free and Open Source libraries, they will give room for more innovation.

=== Custom design approach ===
* [https://www.zerotoasiccourse.com/post/interview-with-james-stine Open Source Standard Cells, Interview with James Stine]

* [https://wiki.f-si.org/index.php?title=Development_of_FreePDK:_An_Open-Source_Process_Design_Kit_for_Advanced_Technology_Nodes Free PDK presentation by Kirti Banushali (FSIC 2019)]

* [https://skywater-pdk.readthedocs.io/en/main/contents/libraries/foundry-provided.html SkyWater 130nm Standard Cell Library]

* [http://www.vlsitechnology.org/html/libraries04.html Standard cell library by Oklahoma State University (OSU)]

* [https://github.com/google/globalfoundries-pdk-libs-gf180mcu_osu_sc Global Foundries 180nm Standard Cell Library by Oklahoma State University (OSU)]

=== Scalable design approach ===
* [https://gitlab.com/Chips4Makers/c4m-flexcell/ FlexCell by Staf Verhaegen]

* [https://gitlab.lip6.fr/vlsi-eda/alliance-check-toolkit/-/tree/main/pdkmaster/C4M.Sky130/libs.ref/StdCellLib FlexCell in SkyWater 130 by Staf Verhaegen]

* [https://codeberg.org/librecell LibreCell by Thomas Kramer]

* [https://github.com/chipforge/StdCellLib Libresilicon Standard Cell Library]

* [https://wiki.f-si.org/index.php?title=Standard_Cell_Library_report Libresilicon Standard Cell Library presented by Hagen Sankowski (FSIC 2022)]

=== Symbolic Approach ===
* [http://www.vlsitechnology.org/index.html Standard Cell Library Design by Graham Petley]

* [https://gitlab.lip6.fr/vlsi-eda/alliance-check-toolkit/-/tree/main/cells/nsxlib2 NSXLIBv2.0 Standard Cell Library by Naohiko Shimizu]

* [https://gitlab.lip6.fr/vlsi-eda/alliance-check-toolkit/-/tree/main/cells/lsxlib LSXLIB Standard Cell Library by Franck Wajsburt]

== References ==
=== Standards and Formats for standard cell description ===
* [https://ieeexplore.ieee.org/document/8938196 1076-2019 - IEEE Standard for VHDL Language Reference Manual]

* [https://ieeexplore.ieee.org/document/1620780 1364-2005 - IEEE Standard for Verilog Hardware Description Language]

* [http://bwrcs.eecs.berkeley.edu/Classes/IcBook/SPICE/ Spice format]

* [https://www.artwork.com/gdsii/gdsii/index.htm GDSII layout format]

* [https://www.synopsys.com/community/interoperability-programs/tap-in.html LIB file format]

=== SW EDA Tools (Free and Open Source ones) ===
* [https://klayout.de/ Klayout for layout edition, DRC (Design Rule Check) and LVS (Layout Versus Schematic) operations]

* [https://ngspice.sourceforge.io/index.html ngspice transistor-level simulator]

* [https://github.com/ghdl/ghdl ghdl VHDL simulator]

* [https://si2.org/oa-tools-utils-libs/ si2 LEF/DEF parsers and drivers]

=== Books ===
* Mead, Carver; Conway, Lynn (1980). Introduction to VLSI systems. Reading, Mass.: Addison-Wesley. ISBN 0201043580. OCLC 4641561

* [https://www.rulabinsky.com/cavd/text/chapc.html Computer Aids for VLSI Design, Steven M. Rubin, 1994]

* Sung-Mo Kang, Yusuf Leblebici, CMOS Digital Integrated Circuits, Analysis and Design, Mac Graw Hill, 2003

* Yannis Tsividis and Colin McAndrew, Operation and Modeling of the MOS Transistor, Third edition, Oxford University Press, 2011.

* Yuhua Cheng and Chenming Hu, MOSFET modeling and BSIM3 User's guide, Kluwer Academic Publisher, 1999

* Jan M. Rabey, Anantha Chandrakasan and Borivoje Nikolic, Digital Integrated Circuits, A design perspective, Prentice Hall, 2003

* Naveed Sherwani, Algorithms for VLSI Physical Design Automation, Kluwer Academic Publisher, 2004

Main Page

2023-09-28T14:10:24Z

Mmlouerat: /* GoIT results */

[[File:GoIT_logo_1700px.png|thumb|Logo of the '''Go IT!''' project.]]

The '''Go IT!''' is an EU ''Coordination and Support Action (CSA)'' about ''Open Source Hardware for ultra-low-power, secure processors'' funded under [https://research-and-innovation.ec.europa.eu/funding/funding-opportunities/funding-programmes-and-open-calls/horizon-europe/cluster-4-digital-industry-and-space_en cluster 4 (Digital, Industry and Space)], of [https://op.europa.eu/en/web/eu-law-and-publications/publication-detail/-/publication/3c6ffd74-8ac3-11eb-b85c-01aa75ed71a1 Horizon Europe]. The project was submitted on [https://wiki.f-si.org/index.php?title=Horizon_2021_Coordination_and_Support_Action_(CSA)_proposal October 21 2021], was awarded on March 18 2022 and started on September 1 2022. Its planned duration is three years. The project number (ID) is 101070660.

=Proposal short summary=
Europe's IT hardware development is constantly challenged by outrageously expensive development tools, legal constraints like NDAs or patents, lock-in threats, dependency from external vendors or supply chains and foreign political events. Europe’s digital infrastructure (from consumer to critical appliances) is heavily relying on foreign closed-source chips which are literally black-boxes which may (and have been proven to) contain malicious features. This situation makes the hardware development expensive
and inefficient, and undermines the very principles of sovereignty, resilience and re-usability. Open-source silicon chips, which are open in their entirety, i.e. down to the physical layout, carry the potential of catapulting Europe into a renaissance of digital technology. Several challenges are on the way, many of which will require the participation of the stakeholders (from the fertile ground made of “nerdy” hobbyists and makers who are the early protagonists of the scene, all the way up to large enterprises), as well as the participation of policymakers and regulatory bodies. The road ahead is steep, but rich of rewards. Therefore we loudly say: Go IT!

=Proposal manuscript=
The manuscript of the submitted proposal can be downloaded [https://wiki.f-si.org/index.php?title=Horizon_2021_Coordination_and_Support_Action_(CSA)_proposal (here)].

=Goals=
The main goals of the project can be summarized as follows:
# Feedback the policymakers with technical reports and roadmaps
# Facilitate the creation of a complete and complementary know-how for open-source chip design across European universities
# Organize three editions of the Free Silicon Conference
# Develop a GPL-compatible forever-open (copyleft) licence for silicon chips
# Include the available open-source PDK in existing open-source design flows
# Create a repository of open-source EDA tools and hardware blocks
# Package open-source tools into mainstream GNU/Linux distributions
# Disseminate the existing open-source tools and libraries on mainstream channels like Wikipedia
# Promote the concept of open-source silicon chips through the participation at mainstream conferences, talks and paid advertisement
# Contribute to standardization and certification activities for open-source silicon chips

=Consortium=
# Elektronikas un Datorzinatnu Instituts (EDI), Latvia ('''coordinator''')
#* [https://www.edi.lv/en/team/rihards-novickis_eng/ Rihards Novickis], [https://www.edi.lv/en/robotics-and-machine-perception/ department of robotics and machine perception]
# [https://sciences.sorbonne-universite.fr/ Sorbonne Université (SU)], France
#* [https://www.lip6.fr/actualite/personnes-fiche.php?ident=P206 Roselyne Chotin], [https://www.lip6.fr/recherche/team.php?acronyme=CIAN group of Analog and Digital Integrated Circuit (CIAN) at LIP6]
#* [https://www.lip6.fr/actualite/personnes-fiche.php?ident=P109 Jean-Paul Chaput], [https://www.lip6.fr/recherche/team.php?acronyme=CIAN group of Analog and Digital Integrated Circuit (CIAN) at LIP6]
#* [https://www.lip6.fr/actualite/personnes-fiche.php?ident=P98 Marie-Minerve Louerat], [https://www.lip6.fr/recherche/team.php?acronyme=CIAN group of Analog and Digital Integrated Circuit (CIAN) at LIP6, CNRS]
# [https://f-si.it Free Silicon Foundation (I) ETS], Italy
#* [https://orcid.org/0000-0002-1245-4179 Luca Alloatti]
#* [https://libreda.org/ Thomas Kramer]
# Agencia Estatal Consejo Superior de Investigaciones Cientificas (CSIC), Spain
#* [https://orcid.org/0000-0003-1059-5338 Piedad Brox Jiménez], [http://www.imse-cnm.csic.es/home.php Instituto de Microlelectronica de Sevilla]
#* [https://dargcsic.github.io/ David Arroyo Guardeno], [https://www.itefi.csic.es/es Instituto de Tecnologías Físicas y de la Información]
#* [https://orcid.org/0000-0003-3025-5736 Macarena Cristina Martínez Rodríguez], [http://www.imse-cnm.csic.es/home.php Instituto de Microlelectronica de Sevilla]
#* Pablo Navarro Torrero, [http://www.imse-cnm.csic.es/home.php Instituto de Microlelectronica de Sevilla]
# FibraServi (FS), Belgium
#* Staf Verhaegen ([https://fosstodon.org/@Chips4Makers @Chips4Makers@fosstodon.org], [https://gitlab.com/FatsieFS FatsieFS@gitlab])
# G-INP/CIME-P, France
#* Kholdoun Torki, CIME-P and CNRS
#* Jeremy Perret, CIME-P, a team within [http://www.cime.inpg.fr/ CIME Nanotech], a lab from [https://www.grenoble-inp.fr/ G-INP]
#* Aurélien Nicolet, CIME-P, a team within [http://www.cime.inpg.fr/ CIME Nanotech], a lab from [https://www.grenoble-inp.fr/ G-INP]

=Contact=
All the members of the consortium can be contacted at once by writing at ''' mail' 'at' goit-project.eu'''.

=GoIT results=
[[Standard Cell Libraries]]

=See also=
==Related conferences==
* [http://www.wikicfp.com/cfp/servlet/event.showlist?lownerid=183370&ltype=w GOIT's timeline in WikiCFP]
=== 2016 ===
* [https://www.cryptoexperts.com/awacs2016/ AWACS 2016], 8 May 2016, Vienna (Austria)
=== 2019 ===
* [https://www.european-processor-initiative.eu/dissemination-material/ec-workshop-open-source-software-and-hardware/ EC workshop on Open Source], 14-15 November 2019, Brussels (Belgium)
=== 2022 ===
* [https://link.springer.com/conference/applepies APPLEPIES 2022], 26-27 September 2022, Genoa (Italy)
* [https://ieeexplore.ieee.org/xpl/conhome/9978287/proceeding ICCD 2022], 23-26 October 2022, Lake Tahoe (USA)
=== 2023 ===
* [https://dl.acm.org/doi/proceedings/10.1145/3566097 ASPDAC 2023], 16-19 January 2023, Tokyo (Japan)
* [https://summit.openforumeurope.org/ EU Open Source Policy Summit 2023], 3 February 2023, Brussels (Belgium)
* [https://fosdem.org/2023/ FOSDEM 2023], 4 - 5 February 2023, Brussels (Belgium)
* [https://cca.informatik.uni-freiburg.de/mbmv23/ MBMV 2O23], 23-25 March 2023, Freiburg (Germany)
* [https://osda.ws/ OSDA at DATE 2023], during 17-19 April 2023, Antwerp (Belgium)
* [https://ddecs2023.taltech.ee/index.php?page=93 DDECS 2023], 3-5 May 2023, Tallinn (Estonia)
* [https://eupilot.eu/event/open-source-hardware-workshop-23/ OSHW 2023], 9 May 2023, Bologna (Italy)
* [https://www.computingfrontiers.org/2023/program.html ACM 2023], 9-11 May 2023, Bologna (Italy)
* [https://iscas2023.org/ ISCAS 2023], 21-25 May 2023, Monterey (USA)
* [https://mvl.jpn.org/ISMVL2023/], 22-24 May 2023, Matsue (Japan)
* [https://ieeexplore.ieee.org/xpl/conhome/10173930/proceeding?isnumber=10173940&sortType=vol-only-seq&searchWithin=risc-v ETS 2023], 22-26 May 2023, Venice (Italy)
* [https://www.glsvlsi.org/program.html GLSVLSI 2023], 5-7 June 2023, Tennessee (USA)
* [https://riscv-europe.org/ RISC-V Summit Europe], 5-9 June 2023, Barcelona (Spain)
* [https://mclabservices.di.uniroma1.it/iwasi/2023/programme.php IWASI 2023], 8-9 June 2023, Bari (Italy)
* [https://www.dac.com/ DAC 2023], 9-13 June 2023, San Francisco (USA)
* [https://www.aicas2023.org/ AICAS 2023], 11-13 June 2023, Hangzhou (China)
* [https://www.gdr-soc.cnrs.fr/ GDR SoC2], 12-14 June 2023, Lyon (France)
* [http://prime-conference.org/ PRIME], 18-21 June 2023, Valencia (Spain)
* [https://www.ufrgs.br/isvlsi2023/ ISVLSI 2023], 20-23 June 2023, Iguazu Falls (Brazil)
* [https://ieee-cas.org/event/conference/2023-ieee-21st-interregional-newcas-conference NEWCAS], 26-28 June 2023, Edinburgh (Scotland)
* [http://mpsoc-forum.org/ MPSOC], 25-30 June 2023, Helena, Montana (USA)
* [https://www.mixdes.org/Mixdes3/tekst/view/about MIXDES], 29 June - 1 July 2023, Krakow (Poland)
* [https://samos-conference.com/wp/wp-content/uploads/2023/Program%202023.htm SAMOS 2023], 2-6 July 2023, Samos (Greece)
* [https://smacd-conference.org/ SMACD], 3-5 July 2023, Madeira Island (Portugal)
* [https://smacd-conference.org/call-for-competition/ SMACD EDA competition], 3-5 July 2023, Madeira Island (Portugal)
* [https://wiki.f-si.org/index.php/FSiC2023 FSIC 2023], 10-12 July 2023, Paris (France)
* [https://www.asap2023.org/program/agenda ASAP 2023], 19-21 July 2023, Porto (Portugal)
* [https://dsd-seaa2023.com/ DSD-SEAA 2023], 6-8 September 2023, Durres (Albania)
* [https://www.sistemacongressi.com/elenco-eventi/essderc-esscirc-2023 ESSDERC-ESSCIRC], 11-14 September 2023, Lisbon (Portugal)
* [https://www.fdl-conference.com/program.html#researchpapersdetails FDL 2023], 13-15 September 2023, Turin (Italy)
* [https://sites.google.com/view/vlsi-soc2023/home VLSI-SOC 2023], 16-18 October 2023, Dubai (UAE)
* [https://iccad.com/ ICCAD 2023], 29 October - 2 November 2023, San Francisco (USA)
* [https://dcis2023.uma.es/ DCIS 2023], 15-17 November 2023, Málaga (Spain), Special Session "RISC-V and Open hardware: research, training and innovation towards Open-source Hw/Sw"

=== 2024 ===
* [https://www.isscc.org/ ISSCC 2024], 18-22 February 2024, San Francisco (USA)
* [https://www.date-conference.com/ DATE 2024], 25-27 March 2024, Valencia, Spain

== Security and cybersecurity events ==
Below we list some major conferences in security and cybersecurity that have included contributions about RISC-V or open hardware in the past:
* [https://www.usenix.org/ USENIX], (Costan, Lebedev, and Devadas 2016), (Barral et al. 2019), (Schrammel et al. 2020), (Bahmani et al. 2021), etc.
* [https://ieeexplore.ieee.org/xpl/conhome/10179215/proceeding IEEE Symposium on Security and Privacy 2023], 21-15 May 2023, San Francisco (USA)
* [https://dl.acm.org/doi/proceedings/10.1145/3579856 ASIA CCS'23], 10-14 July 2023, Melbourne (Australia)
* [https://www.ares-conference.eu/ ARES 2023], 29 August - September 1 2023, Benevento (Italy)
* [https://ches.iacr.org/2023/forum.php CHES 2023], 10-14 September 2023, Prague (Czech Republic)
* [https://esorics2023.org/program/workshop/ ESORICS 2023], 28-29 September 2023, The Hague (Netherlands)
* [https://iccconference.org/ ICCC 2023], 30 October - 2 November 2023, Washington DC (USA)

==Related EU projects==
* [https://eupilot.eu/ The European PILOT] aims at demonstrating an all European technology by including open source hardware for HPC
* [https://www.european-processor-initiative.eu/ The European Processor Initiative (EPI)] aims at designing and implementing a roadmap for a new family of low-power European processors for extreme scale computing, high-performance Big-Data and a range of emerging applications
* [https://eupex.eu/ The European Pilot for Exascale] aims at building and validating the first HPC platform integrating the full spectrum of European HPC technologies, from architecture, processors and interconnect to system software.
* [https://www.montblanc-project.eu/ The European Modular and Power-Efficient HPC Processor] aimed to start developing building blocks (IPs) for an HPC processor

=Newsletter=
[https://nextcloud.goit-project.eu/s/FwDoqNqcPQgyJwP Newsletter "Open initiatives in hardware security"] linked to Milestone 6.1 is available
[[File:GoIT_Newsletter.png|thumb|Newsletter of the '''Go IT!''' project.]]

Main Page

2023-09-28T14:06:22Z

Mmlouerat:

[[File:GoIT_logo_1700px.png|thumb|Logo of the '''Go IT!''' project.]]

The '''Go IT!''' is an EU ''Coordination and Support Action (CSA)'' about ''Open Source Hardware for ultra-low-power, secure processors'' funded under [https://research-and-innovation.ec.europa.eu/funding/funding-opportunities/funding-programmes-and-open-calls/horizon-europe/cluster-4-digital-industry-and-space_en cluster 4 (Digital, Industry and Space)], of [https://op.europa.eu/en/web/eu-law-and-publications/publication-detail/-/publication/3c6ffd74-8ac3-11eb-b85c-01aa75ed71a1 Horizon Europe]. The project was submitted on [https://wiki.f-si.org/index.php?title=Horizon_2021_Coordination_and_Support_Action_(CSA)_proposal October 21 2021], was awarded on March 18 2022 and started on September 1 2022. Its planned duration is three years. The project number (ID) is 101070660.

=Proposal short summary=
Europe's IT hardware development is constantly challenged by outrageously expensive development tools, legal constraints like NDAs or patents, lock-in threats, dependency from external vendors or supply chains and foreign political events. Europe’s digital infrastructure (from consumer to critical appliances) is heavily relying on foreign closed-source chips which are literally black-boxes which may (and have been proven to) contain malicious features. This situation makes the hardware development expensive
and inefficient, and undermines the very principles of sovereignty, resilience and re-usability. Open-source silicon chips, which are open in their entirety, i.e. down to the physical layout, carry the potential of catapulting Europe into a renaissance of digital technology. Several challenges are on the way, many of which will require the participation of the stakeholders (from the fertile ground made of “nerdy” hobbyists and makers who are the early protagonists of the scene, all the way up to large enterprises), as well as the participation of policymakers and regulatory bodies. The road ahead is steep, but rich of rewards. Therefore we loudly say: Go IT!

=Proposal manuscript=
The manuscript of the submitted proposal can be downloaded [https://wiki.f-si.org/index.php?title=Horizon_2021_Coordination_and_Support_Action_(CSA)_proposal (here)].

=Goals=
The main goals of the project can be summarized as follows:
# Feedback the policymakers with technical reports and roadmaps
# Facilitate the creation of a complete and complementary know-how for open-source chip design across European universities
# Organize three editions of the Free Silicon Conference
# Develop a GPL-compatible forever-open (copyleft) licence for silicon chips
# Include the available open-source PDK in existing open-source design flows
# Create a repository of open-source EDA tools and hardware blocks
# Package open-source tools into mainstream GNU/Linux distributions
# Disseminate the existing open-source tools and libraries on mainstream channels like Wikipedia
# Promote the concept of open-source silicon chips through the participation at mainstream conferences, talks and paid advertisement
# Contribute to standardization and certification activities for open-source silicon chips

=Consortium=
# Elektronikas un Datorzinatnu Instituts (EDI), Latvia ('''coordinator''')
#* [https://www.edi.lv/en/team/rihards-novickis_eng/ Rihards Novickis], [https://www.edi.lv/en/robotics-and-machine-perception/ department of robotics and machine perception]
# [https://sciences.sorbonne-universite.fr/ Sorbonne Université (SU)], France
#* [https://www.lip6.fr/actualite/personnes-fiche.php?ident=P206 Roselyne Chotin], [https://www.lip6.fr/recherche/team.php?acronyme=CIAN group of Analog and Digital Integrated Circuit (CIAN) at LIP6]
#* [https://www.lip6.fr/actualite/personnes-fiche.php?ident=P109 Jean-Paul Chaput], [https://www.lip6.fr/recherche/team.php?acronyme=CIAN group of Analog and Digital Integrated Circuit (CIAN) at LIP6]
#* [https://www.lip6.fr/actualite/personnes-fiche.php?ident=P98 Marie-Minerve Louerat], [https://www.lip6.fr/recherche/team.php?acronyme=CIAN group of Analog and Digital Integrated Circuit (CIAN) at LIP6, CNRS]
# [https://f-si.it Free Silicon Foundation (I) ETS], Italy
#* [https://orcid.org/0000-0002-1245-4179 Luca Alloatti]
#* [https://libreda.org/ Thomas Kramer]
# Agencia Estatal Consejo Superior de Investigaciones Cientificas (CSIC), Spain
#* [https://orcid.org/0000-0003-1059-5338 Piedad Brox Jiménez], [http://www.imse-cnm.csic.es/home.php Instituto de Microlelectronica de Sevilla]
#* [https://dargcsic.github.io/ David Arroyo Guardeno], [https://www.itefi.csic.es/es Instituto de Tecnologías Físicas y de la Información]
#* [https://orcid.org/0000-0003-3025-5736 Macarena Cristina Martínez Rodríguez], [http://www.imse-cnm.csic.es/home.php Instituto de Microlelectronica de Sevilla]
#* Pablo Navarro Torrero, [http://www.imse-cnm.csic.es/home.php Instituto de Microlelectronica de Sevilla]
# FibraServi (FS), Belgium
#* Staf Verhaegen ([https://fosstodon.org/@Chips4Makers @Chips4Makers@fosstodon.org], [https://gitlab.com/FatsieFS FatsieFS@gitlab])
# G-INP/CIME-P, France
#* Kholdoun Torki, CIME-P and CNRS
#* Jeremy Perret, CIME-P, a team within [http://www.cime.inpg.fr/ CIME Nanotech], a lab from [https://www.grenoble-inp.fr/ G-INP]
#* Aurélien Nicolet, CIME-P, a team within [http://www.cime.inpg.fr/ CIME Nanotech], a lab from [https://www.grenoble-inp.fr/ G-INP]

=Contact=
All the members of the consortium can be contacted at once by writing at ''' mail' 'at' goit-project.eu'''.

=GoIT results=
[[Open Source Standard Cell Libraries]]

=See also=
==Related conferences==
* [http://www.wikicfp.com/cfp/servlet/event.showlist?lownerid=183370&ltype=w GOIT's timeline in WikiCFP]
=== 2016 ===
* [https://www.cryptoexperts.com/awacs2016/ AWACS 2016], 8 May 2016, Vienna (Austria)
=== 2019 ===
* [https://www.european-processor-initiative.eu/dissemination-material/ec-workshop-open-source-software-and-hardware/ EC workshop on Open Source], 14-15 November 2019, Brussels (Belgium)
=== 2022 ===
* [https://link.springer.com/conference/applepies APPLEPIES 2022], 26-27 September 2022, Genoa (Italy)
* [https://ieeexplore.ieee.org/xpl/conhome/9978287/proceeding ICCD 2022], 23-26 October 2022, Lake Tahoe (USA)
=== 2023 ===
* [https://dl.acm.org/doi/proceedings/10.1145/3566097 ASPDAC 2023], 16-19 January 2023, Tokyo (Japan)
* [https://summit.openforumeurope.org/ EU Open Source Policy Summit 2023], 3 February 2023, Brussels (Belgium)
* [https://fosdem.org/2023/ FOSDEM 2023], 4 - 5 February 2023, Brussels (Belgium)
* [https://cca.informatik.uni-freiburg.de/mbmv23/ MBMV 2O23], 23-25 March 2023, Freiburg (Germany)
* [https://osda.ws/ OSDA at DATE 2023], during 17-19 April 2023, Antwerp (Belgium)
* [https://ddecs2023.taltech.ee/index.php?page=93 DDECS 2023], 3-5 May 2023, Tallinn (Estonia)
* [https://eupilot.eu/event/open-source-hardware-workshop-23/ OSHW 2023], 9 May 2023, Bologna (Italy)
* [https://www.computingfrontiers.org/2023/program.html ACM 2023], 9-11 May 2023, Bologna (Italy)
* [https://iscas2023.org/ ISCAS 2023], 21-25 May 2023, Monterey (USA)
* [https://mvl.jpn.org/ISMVL2023/], 22-24 May 2023, Matsue (Japan)
* [https://ieeexplore.ieee.org/xpl/conhome/10173930/proceeding?isnumber=10173940&sortType=vol-only-seq&searchWithin=risc-v ETS 2023], 22-26 May 2023, Venice (Italy)
* [https://www.glsvlsi.org/program.html GLSVLSI 2023], 5-7 June 2023, Tennessee (USA)
* [https://riscv-europe.org/ RISC-V Summit Europe], 5-9 June 2023, Barcelona (Spain)
* [https://mclabservices.di.uniroma1.it/iwasi/2023/programme.php IWASI 2023], 8-9 June 2023, Bari (Italy)
* [https://www.dac.com/ DAC 2023], 9-13 June 2023, San Francisco (USA)
* [https://www.aicas2023.org/ AICAS 2023], 11-13 June 2023, Hangzhou (China)
* [https://www.gdr-soc.cnrs.fr/ GDR SoC2], 12-14 June 2023, Lyon (France)
* [http://prime-conference.org/ PRIME], 18-21 June 2023, Valencia (Spain)
* [https://www.ufrgs.br/isvlsi2023/ ISVLSI 2023], 20-23 June 2023, Iguazu Falls (Brazil)
* [https://ieee-cas.org/event/conference/2023-ieee-21st-interregional-newcas-conference NEWCAS], 26-28 June 2023, Edinburgh (Scotland)
* [http://mpsoc-forum.org/ MPSOC], 25-30 June 2023, Helena, Montana (USA)
* [https://www.mixdes.org/Mixdes3/tekst/view/about MIXDES], 29 June - 1 July 2023, Krakow (Poland)
* [https://samos-conference.com/wp/wp-content/uploads/2023/Program%202023.htm SAMOS 2023], 2-6 July 2023, Samos (Greece)
* [https://smacd-conference.org/ SMACD], 3-5 July 2023, Madeira Island (Portugal)
* [https://smacd-conference.org/call-for-competition/ SMACD EDA competition], 3-5 July 2023, Madeira Island (Portugal)
* [https://wiki.f-si.org/index.php/FSiC2023 FSIC 2023], 10-12 July 2023, Paris (France)
* [https://www.asap2023.org/program/agenda ASAP 2023], 19-21 July 2023, Porto (Portugal)
* [https://dsd-seaa2023.com/ DSD-SEAA 2023], 6-8 September 2023, Durres (Albania)
* [https://www.sistemacongressi.com/elenco-eventi/essderc-esscirc-2023 ESSDERC-ESSCIRC], 11-14 September 2023, Lisbon (Portugal)
* [https://www.fdl-conference.com/program.html#researchpapersdetails FDL 2023], 13-15 September 2023, Turin (Italy)
* [https://sites.google.com/view/vlsi-soc2023/home VLSI-SOC 2023], 16-18 October 2023, Dubai (UAE)
* [https://iccad.com/ ICCAD 2023], 29 October - 2 November 2023, San Francisco (USA)
* [https://dcis2023.uma.es/ DCIS 2023], 15-17 November 2023, Málaga (Spain), Special Session "RISC-V and Open hardware: research, training and innovation towards Open-source Hw/Sw"

=== 2024 ===
* [https://www.isscc.org/ ISSCC 2024], 18-22 February 2024, San Francisco (USA)
* [https://www.date-conference.com/ DATE 2024], 25-27 March 2024, Valencia, Spain

== Security and cybersecurity events ==
Below we list some major conferences in security and cybersecurity that have included contributions about RISC-V or open hardware in the past:
* [https://www.usenix.org/ USENIX], (Costan, Lebedev, and Devadas 2016), (Barral et al. 2019), (Schrammel et al. 2020), (Bahmani et al. 2021), etc.
* [https://ieeexplore.ieee.org/xpl/conhome/10179215/proceeding IEEE Symposium on Security and Privacy 2023], 21-15 May 2023, San Francisco (USA)
* [https://dl.acm.org/doi/proceedings/10.1145/3579856 ASIA CCS'23], 10-14 July 2023, Melbourne (Australia)
* [https://www.ares-conference.eu/ ARES 2023], 29 August - September 1 2023, Benevento (Italy)
* [https://ches.iacr.org/2023/forum.php CHES 2023], 10-14 September 2023, Prague (Czech Republic)
* [https://esorics2023.org/program/workshop/ ESORICS 2023], 28-29 September 2023, The Hague (Netherlands)
* [https://iccconference.org/ ICCC 2023], 30 October - 2 November 2023, Washington DC (USA)

==Related EU projects==
* [https://eupilot.eu/ The European PILOT] aims at demonstrating an all European technology by including open source hardware for HPC
* [https://www.european-processor-initiative.eu/ The European Processor Initiative (EPI)] aims at designing and implementing a roadmap for a new family of low-power European processors for extreme scale computing, high-performance Big-Data and a range of emerging applications
* [https://eupex.eu/ The European Pilot for Exascale] aims at building and validating the first HPC platform integrating the full spectrum of European HPC technologies, from architecture, processors and interconnect to system software.
* [https://www.montblanc-project.eu/ The European Modular and Power-Efficient HPC Processor] aimed to start developing building blocks (IPs) for an HPC processor

=Newsletter=
[https://nextcloud.goit-project.eu/s/FwDoqNqcPQgyJwP Newsletter "Open initiatives in hardware security"] linked to Milestone 6.1 is available
[[File:GoIT_Newsletter.png|thumb|Newsletter of the '''Go IT!''' project.]]

Main Page

2023-01-12T09:06:14Z

Mmlouerat: /* Consortium */

[[File:GoIT_logo_1700px.png|thumb|Logo of the '''Go IT!''' project.]]

The '''Go IT!''' is an EU ''Coordination and Support Action (CSA)'' funded under [https://research-and-innovation.ec.europa.eu/funding/funding-opportunities/funding-programmes-and-open-calls/horizon-europe/cluster-4-digital-industry-and-space_en cluster 4 (Digital, Industry and Space)], of [https://op.europa.eu/en/web/eu-law-and-publications/publication-detail/-/publication/3c6ffd74-8ac3-11eb-b85c-01aa75ed71a1 Horizon Europe]. The project was submitted on [https://wiki.f-si.org/index.php?title=Horizon_2021_Coordination_and_Support_Action_(CSA)_proposal October 21 2021], was awarded on March 18 2022 and started on September 1 2022. Its planned duration is three years. The project number (ID) is 101070660.

=Proposal short summary=
Europe's IT hardware development is constantly challenged by outrageously expensive development tools, legal constraints like NDAs or patents, lock-in threats, dependency from external vendors or supply chains and foreign political events. Europe’s digital infrastructure (from consumer to critical appliances) is heavily relying on foreign closed-source chips which are literally black-boxes which may (and have been proven to) contain malicious features. This situation makes the hardware development expensive
and inefficient, and undermines the very principles of sovereignty, resilience and re-usability. Open-source silicon chips, which are open in their entirety, i.e. down to the physical layout, carry the potential of catapulting Europe into a renaissance of digital technology. Several challenges are on the way, many of which will require the participation of the stakeholders (from the fertile ground made of “nerdy” hobbyists and makers who are the early protagonists of the scene, all the way up to large enterprises), as well as the participation of policymakers and regulatory bodies. The road ahead is steep, but rich of rewards. Therefore we loudly say: Go IT!

=Proposal manuscript=
The manuscript of the submitted proposal can be downloaded [https://wiki.f-si.org/index.php?title=Horizon_2021_Coordination_and_Support_Action_(CSA)_proposal (here)].

=Goals=
The main goals of the project can be summarized as follows:
# Feedback the policymakers with technical reports and roadmaps
# Facilitate the creation of a complete and complementary know-how for open-source chip design across European universities
# Organize three editions of the Free Silicon Conference
# Develop a GPL-compatible forever-open (copyleft) licence for silicon chips
# Include the available open-source PDK in existing open-source design flows
# Create a repository of open-source EDA tools and hardware blocks
# Package open-source tools into mainstream GNU/Linux distributions
# Disseminate the existing open-source tools and libraries on mainstream channels like Wikipedia
# Promote the concept of open-source silicon chips through the participation at mainstream conferences, talks and paid advertisement
# Contribute to standardization and certification activities for open-source silicon chips

=Consortium=
# Elektronikas un Datorzinatnu Instituts (EDI), Latvia ('''coordinator''')
#* [https://www.edi.lv/en/team/rihards-novickis_eng/ Rihards Novickis], [https://www.edi.lv/en/robotics-and-machine-perception/ department of robotics and machine perception]
# [https://sciences.sorbonne-universite.fr/ Sorbonne Université (SU)], France
#* [https://www.lip6.fr/actualite/personnes-fiche.php?ident=P206 Roselyne Chotin], [https://www.lip6.fr/recherche/team.php?acronyme=CIAN group of Analog and Digital Integrated Circuit (CIAN) at LIP6]
#* [https://www.lip6.fr/actualite/personnes-fiche.php?ident=P109 Jean-Paul Chaput], [https://www.lip6.fr/recherche/team.php?acronyme=CIAN group of Analog and Digital Integrated Circuit (CIAN) at LIP6]
#* [https://www.lip6.fr/actualite/personnes-fiche.php?ident=P98 Marie-Minerve Louerat], [https://www.lip6.fr/recherche/team.php?acronyme=CIAN group of Analog and Digital Integrated Circuit (CIAN) at LIP6, CNRS]
# CIME-P, France
#* Kholdoun Torki, CIME-P and CNRS
#* Jeremy Perret, CIME-P, a team within [http://www.cime.inpg.fr/ CIME Nanotech], a lab from [https://www.grenoble-inp.fr/ G-INP]
#* Aurélien Nicolet, CIME-P, a team within [http://www.cime.inpg.fr/ CIME Nanotech], a lab from [https://www.grenoble-inp.fr/ G-INP]
# [https://f-si.it Free Silicon Foundation (I) ETS], Italy
#* [https://orcid.org/0000-0002-1245-4179 Luca Alloatti]
#* [https://libreda.org/ Thomas Kramer]
# Agencia Estatal Consejo Superior de Investigaciones Cientificas (CSIC), Spain
#* [https://orcid.org/0000-0003-1059-5338 Piedad Brox Jiménez], [http://www.imse-cnm.csic.es/home.php Instituto de Microlelectronica de Sevilla]
#* [https://dargcsic.github.io/ David Arroyo Guardeno], [https://www.itefi.csic.es/es Instituto de Tecnologías Físicas y de la Información]
#* Pablo Navarro Torrero, [http://www.imse-cnm.csic.es/home.php Instituto de Microlelectronica de Sevilla]
# FibraServi (FS), Belgium
#* Staf Verhaegen ([https://fosstodon.org/@Chips4Makers @Chips4Makers@fosstodon.org], [https://gitlab.com/FatsieFS FatsieFS@gitlab])

=Contact=
All the members of the consortium can be contacted at once by writing at ''' mail' 'at' goit-project.eu'''.

=See also=
==Related EU projects==
* [https://eupilot.eu/ The European PILOT] aims at demonstrating an all European technology by including open source hardware for HPC
* [https://www.european-processor-initiative.eu/ The European Processor Initiative (EPI)] aims at designing and implementing a roadmap for a new family of low-power European processors for extreme scale computing, high-performance Big-Data and a range of emerging applications
* [https://eupex.eu/ The European Pilot for Exascale] aims at building and validating the first HPC platform integrating the full spectrum of European HPC technologies, from architecture, processors and interconnect to system software.
* [https://www.montblanc-project.eu/ The European Modular and Power-Efficient HPC Processor] aimed to start developing building blocks (IPs) for an HPC processor

Main Page

2023-01-11T17:12:15Z

Mmlouerat: /* Consortium */

[[File:GoIT_logo_1700px.png|thumb|Logo of the '''Go IT!''' project.]]

The '''Go IT!''' is an EU ''Coordination and Support Action (CSA)'' funded under [https://research-and-innovation.ec.europa.eu/funding/funding-opportunities/funding-programmes-and-open-calls/horizon-europe/cluster-4-digital-industry-and-space_en cluster 4 (Digital, Industry and Space)], of [https://op.europa.eu/en/web/eu-law-and-publications/publication-detail/-/publication/3c6ffd74-8ac3-11eb-b85c-01aa75ed71a1 Horizon Europe]. The project was submitted on [https://wiki.f-si.org/index.php?title=Horizon_2021_Coordination_and_Support_Action_(CSA)_proposal October 21 2021], was awarded on March 18 2022 and started on September 1 2022. Its planned duration is three years. The project number (ID) is 101070660.

=Proposal short summary=
Europe's IT hardware development is constantly challenged by outrageously expensive development tools, legal constraints like NDAs or patents, lock-in threats, dependency from external vendors or supply chains and foreign political events. Europe’s digital infrastructure (from consumer to critical appliances) is heavily relying on foreign closed-source chips which are literally black-boxes which may (and have been proven to) contain malicious features. This situation makes the hardware development expensive
and inefficient, and undermines the very principles of sovereignty, resilience and re-usability. Open-source silicon chips, which are open in their entirety, i.e. down to the physical layout, carry the potential of catapulting Europe into a renaissance of digital technology. Several challenges are on the way, many of which will require the participation of the stakeholders (from the fertile ground made of “nerdy” hobbyists and makers who are the early protagonists of the scene, all the way up to large enterprises), as well as the participation of policymakers and regulatory bodies. The road ahead is steep, but rich of rewards. Therefore we loudly say: Go IT!

=Proposal manuscript=
The manuscript of the submitted proposal can be downloaded [https://wiki.f-si.org/index.php?title=Horizon_2021_Coordination_and_Support_Action_(CSA)_proposal (here)].

=Goals=
The main goals of the project can be summarized as follows:
# Feedback the policymakers with technical reports and roadmaps
# Facilitate the creation of a complete and complementary know-how for open-source chip design across European universities
# Organize three editions of the Free Silicon Conference
# Develop a GPL-compatible forever-open (copyleft) licence for silicon chips
# Include the available open-source PDK in existing open-source design flows
# Create a repository of open-source EDA tools and hardware blocks
# Package open-source tools into mainstream GNU/Linux distributions
# Disseminate the existing open-source tools and libraries on mainstream channels like Wikipedia
# Promote the concept of open-source silicon chips through the participation at mainstream conferences, talks and paid advertisement
# Contribute to standardization and certification activities for open-source silicon chips

=Consortium=
# Elektronikas un Datorzinatnu Instituts (EDI), Latvia ('''coordinator''')
#* [https://www.edi.lv/en/team/rihards-novickis_eng/ Rihards Novickis], [https://www.edi.lv/en/robotics-and-machine-perception/ department of robotics and machine perception]
# [https://sciences.sorbonne-universite.fr/ Sorbonne Université (SU)], France
#* [https://www.lip6.fr/actualite/personnes-fiche.php?ident=P206 Roselyne Chotin], [https://www.lip6.fr/recherche/team.php?acronyme=CIAN group of Analog and Digital Integrated Circuit (CIAN) at LIP6]
#* [https://www.lip6.fr/actualite/personnes-fiche.php?ident=P109 Jean-Paul Chaput], [https://www.lip6.fr/recherche/team.php?acronyme=CIAN group of Analog and Digital Integrated Circuit (CIAN) at LIP6]
#* [https://www.lip6.fr/actualite/personnes-fiche.php?ident=P98 Marie-Minerve Louerat], [https://www.lip6.fr/recherche/team.php?acronyme=CIAN group of Analog and Digital Integrated Circuit (CIAN) at LIP6, CNRS]
# CIME-P, France
#* Kholdoun Torki, CNRS
#* Jeremy Perret, CIME-P, a team within [http://www.cime.inpg.fr/ CIME Nanotech], a lab from [https://www.grenoble-inp.fr/ G-INP]
#* Aurélien Nicolet, CIME-P, a team within [http://www.cime.inpg.fr/ CIME Nanotech], a lab from [https://www.grenoble-inp.fr/ G-INP]
# [https://f-si.it Free Silicon Foundation (I) ETS], Italy
#* [https://orcid.org/0000-0002-1245-4179 Luca Alloatti]
#* [https://libreda.org/ Thomas Kramer]
# Agencia Estatal Consejo Superior de Investigaciones Cientificas (CSIC), Spain
#* [https://orcid.org/0000-0003-1059-5338 Piedad Brox Jiménez], [http://www.imse-cnm.csic.es/home.php Instituto de Microlelectronica de Sevilla]
#* [https://dargcsic.github.io/ David Arroyo Guardeno], [https://www.itefi.csic.es/es Instituto de Tecnologías Físicas y de la Información]
#* Pablo Navarro Torrero, [http://www.imse-cnm.csic.es/home.php Instituto de Microlelectronica de Sevilla]
# FibraServi (FS), Belgium
#* Staf Verhaegen ([https://fosstodon.org/@Chips4Makers @Chips4Makers@fosstodon.org], [https://gitlab.com/FatsieFS FatsieFS@gitlab])

=Contact=
All the members of the consortium can be contacted at once by writing at ''' mail' 'at' goit-project.eu'''.

=See also=
==Related EU projects==
* [https://eupilot.eu/ The European PILOT] aims at demonstrating an all European technology by including open source hardware for HPC
* [https://www.european-processor-initiative.eu/ The European Processor Initiative (EPI)] aims at designing and implementing a roadmap for a new family of low-power European processors for extreme scale computing, high-performance Big-Data and a range of emerging applications
* [https://eupex.eu/ The European Pilot for Exascale] aims at building and validating the first HPC platform integrating the full spectrum of European HPC technologies, from architecture, processors and interconnect to system software.
* [https://www.montblanc-project.eu/ The European Modular and Power-Efficient HPC Processor] aimed to start developing building blocks (IPs) for an HPC processor