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Logo of the Go IT! project.

The Go IT! is an EU Coordination and Support Action (CSA) about Open Source Hardware for ultra-low-power, secure processors funded under cluster 4 (Digital, Industry and Space), of Horizon Europe. The project was submitted on October 21 2021, was awarded on March 18 2022 and started on September 1 2022. Its planned duration is three years. The project number (ID) is 101070660.

Proposal short summary

Europe's IT hardware development is constantly challenged by outrageously expensive development tools, legal constraints like NDAs or patents, lock-in threats, dependency from external vendors or supply chains and foreign political events. Europe’s digital infrastructure (from consumer to critical appliances) is heavily relying on foreign closed-source chips which are literally black-boxes which may (and have been proven to) contain malicious features. This situation makes the hardware development expensive and inefficient, and undermines the very principles of sovereignty, resilience and re-usability. Open-source silicon chips, which are open in their entirety, i.e. down to the physical layout, carry the potential of catapulting Europe into a renaissance of digital technology. Several challenges are on the way, many of which will require the participation of the stakeholders (from the fertile ground made of “nerdy” hobbyists and makers who are the early protagonists of the scene, all the way up to large enterprises), as well as the participation of policymakers and regulatory bodies. The road ahead is steep, but rich of rewards. Therefore we loudly say: Go IT!

Proposal manuscript

The manuscript of the submitted proposal can be downloaded (here).

Goals

The main goals of the project can be summarized as follows:

1. Feedback the policymakers with technical reports and roadmaps
2. Facilitate the creation of a complete and complementary know-how for open-source chip design across European universities
3. Organize three editions of the Free Silicon Conference
4. Develop a GPL-compatible forever-open (copyleft) licence for silicon chips
5. Include the available open-source PDK in existing open-source design flows
6. Create a repository of open-source EDA tools and hardware blocks
7. Package open-source tools into mainstream GNU/Linux distributions
8. Disseminate the existing open-source tools and libraries on mainstream channels like Wikipedia
9. Promote the concept of open-source silicon chips through the participation at mainstream conferences, talks and paid advertisement
10. Contribute to standardization and certification activities for open-source silicon chips

Consortium

1. Elektronikas un Datorzinatnu Instituts (EDI), Latvia (coordinator)
   • Rihards Novickis, department of robotics and machine perception
2. Sorbonne Université (SU), France
   • Roselyne Chotin, group of Analog and Digital Integrated Circuit (CIAN) at LIP6
   • Jean-Paul Chaput, group of Analog and Digital Integrated Circuit (CIAN) at LIP6
   • Marie-Minerve Louerat, group of Analog and Digital Integrated Circuit (CIAN) at LIP6, CNRS
3. Free Silicon Foundation (I) ETS, Italy
   • Luca Alloatti
   • Thomas Kramer
4. Agencia Estatal Consejo Superior de Investigaciones Cientificas (CSIC), Spain
   • Piedad Brox Jiménez, Instituto de Microlelectronica de Sevilla
   • David Arroyo Guardeno, Instituto de Tecnologías Físicas y de la Información
   • Macarena Cristina Martínez Rodríguez, Instituto de Microlelectronica de Sevilla
   • Pablo Navarro Torrero, Instituto de Microlelectronica de Sevilla
5. FibraServi (FS), Belgium
   • Staf Verhaegen (@Chips4Makers@fosstodon.org, FatsieFS@gitlab)
6. G-INP/CIME-P, France
   • Kholdoun Torki, CIME-P and CNRS
   • Jeremy Perret, CIME-P, a team within CIME Nanotech, a lab from G-INP
   • Aurélien Nicolet, CIME-P, a team within CIME Nanotech, a lab from G-INP

Contact

All the members of the consortium can be contacted at once by writing at mail' 'at' goit-project.eu.

See also

Related conferences

• GOIT's timeline in WikiCFP

2016

• [1], 8 May 2016, Vienna (Austria)

2019

• [2], 14-15 November 2019, Brussels (Belgium)

2022

• [3], 26-27 September 2022, Genoa (Italy)
• [4], 23-26 October 2022, Lake Tahoe (USA)

2023

• [5], 16-19 January 2023, Tokyo (Japan)
• EU Open Source Policy Summit 2023, 3 February 2023, Brussels (Belgium)
• FOSDEM 2023, 4 - 5 February 2023, Brussels (Belgium)
• [6], 23-25 March 2023, Freiburg (Germany)
• OSDA at DATE 2023, during 17-19 April 2023, Antwerp (Belgium)
• [7], 3-5 May 2023, Tallinn (Estonia)
• [8], 9 May 2023, Bologna (Italy)
• [9], 9-11 May 2023, Bologna (Italy)
• ISCAS 2023, 21-25 May 2023, Monterey (USA)
• [10], 22-24 May 2023, Matsue (Japan)
• [11], 22-26 May 2023, Venice (Italy)
• [12], 5-7 June 2023, Tennessee (USA)
• RISC-V Summit Europe, 5-9 June 2023, Barcelona (Spain)
• [13], 8-9 June 2023, Bari (Italy)
• [14], 9-13 June 2023, San Francisco (USA)
• [15], 11-13 June 2023, Hangzhou (China)
• GDR SoC2, 12-14 June 2023, Lyon (France)
• PRIME, 18-21 June 2023, Valencia (Spain)
• [16], 20-23 June 2023, Iguazu Falls (Brazil)
• NEWCAS, 26-28 June 2023, Edinburgh (Scotland)
• MPSOC, 25-30 June 2023, Helena, Montana (USA)
• MIXDES, 29 June - 1 July 2023, Krakow (Poland)
• [17], 2-6 July 2023, Samos (Greece)
• SMACD, 3-5 July 2023, Madeira Island (Portugal)
• SMACD EDA competition, 3-5 July 2023, Madeira Island (Portugal)
• FSIC 2023, 10-12 July 2023, Paris (France)
• [18], 19-21 July 2023, Porto (Portugal)
• [19], 6-8 September 2023, Durres (Albania)
• ESSDERC-ESSCIRC, 11-14 September 2023, Lisbon (Portugal)
• [20], 13-15 September 2023, Turin (Italy)
• [21], 16-18 October 2023, Dubai (UAE)
• [22], 29 October - 2 November 2023, San Francisco (USA)
• DCIS 2023, 15-17 November 2023, Málaga (Spain), Special Session "RISC-V and Open hardware: research, training and innovation towards Open-source Hw/Sw"

2024

• [23], 18-22 February 2024, San Francisco (USA)
• [24], 25-27 March 2024, Valencia, Spain

Related EU projects

• The European PILOT aims at demonstrating an all European technology by including open source hardware for HPC
• The European Processor Initiative (EPI) aims at designing and implementing a roadmap for a new family of low-power European processors for extreme scale computing, high-performance Big-Data and a range of emerging applications
• The European Pilot for Exascale aims at building and validating the first HPC platform integrating the full spectrum of European HPC technologies, from architecture, processors and interconnect to system software.
• The European Modular and Power-Efficient HPC Processor aimed to start developing building blocks (IPs) for an HPC processor