Standard Cell Libraries

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Free and Open Source Standard Cell Libraries

In this page, LIP6, (Sorbonne Université & CNRS) wishes to present a survey of the existing open-source standard-cell libraries. This study is part of the GoIT project. This page will be regularly updated, since new Open PDK projects are ongoing, such as the IHP Open PDK.

Different formats and views

A library of Standard Cells provides different descriptions (or views) of each cell. These descriptions are based on different formats and languages. To be compliant with a digital design flow, a cell has to provide at least 3 views:

  • Logical level model. IIt is the model of the functional behaviour represented by a boolean logic function. The model uses the VHDL or the Verilog language. The cell's logic function is used for logic synthesis of a digital circuit. The behavioural model is compatible with event driven simulator for functional verification of a digital circuit. The interface of the cell model (input, output) is used by the place and root operation in the circuit design flow (i.e. circuit layout);
  • Transistor level netlist. It is the description of the interconnection of the set of transistors required to generate the logic behavior. It is written in spice format. This model is compatible with transistor-level simulation with ngspice, which may be used for timing characterization of the cell;
  • Layout description. It is written according to the GDSII format. It is used by place and route software tools to create the layout of the digital circuit that will be sent by the designer for fabrication in a foundry.

Depending on the cell use, other descriptions may also be required:

  • Schematic representation of the boolean logic function, for circuit schematic capture;
  • Layout and design abstract information (Lef, Def), used by place and route software tools;
  • Timing information, Liberty file (lib), used by logic synthesizers and static timing analyzers;
  • Post-layout transistor spice netlist including parasitics, used by static timing analyzer and performance estimation (power, timing, area) tools.

Layout Design approaches

Different approaches are used to generate the layout of standard cells, which are:

  • Custom design. For each target process, the layout is edited from scratch with the help of a layout editor and a Design Rule Checker (DRC), such as KLayout.
  • Scalable design. The layout is generated for each target process. The designer of the cell provides a procedural description of the layout (Python scripts can be used).
  • Symbolic approach. Symbolic Layout is a way of making the layout of a chip independent of the target technological node. Symbolic layout is created by drawing the polygons in a blank unit called the lambda. Then, the value of the lambda is calculated for the target technology so that the layout fits its particular design rules. The symbolic layout is translated to real layout, according to the lambda value. This approach was first introduced by Mead and Conway. The symbolic layout allows the designer to show a physical view even when the PDK, and its associated Design Rules Manual (DRM), are distributed subject to NDA.

Existing Open Source Libraries of Standard Cells

There are some open source libraries available today. They are listed below, with available download link, depending on the approach they are using for layout generation. They have already inspired a lot of EDA software and circuit designers, not to mention the thousands of VLSI students. As Free and Open Source libraries, they will give room for more innovation.

Custom design approach

Scalable design approach

Symbolic Approach


Standards and Formats for standard cell description

SW EDA Tools (Free and Open Source ones)


  • Mead, Carver; Conway, Lynn (1980). Introduction to VLSI systems. Reading, Mass.: Addison-Wesley. ISBN 0201043580. OCLC 4641561
  • Sung-Mo Kang, Yusuf Leblebici, CMOS Digital Integrated Circuits, Analysis and Design, Mac Graw Hill, 2003
  • Yannis Tsividis and Colin McAndrew, Operation and Modeling of the MOS Transistor, Third edition, Oxford University Press, 2011.
  • Yuhua Cheng and Chenming Hu, MOSFET modeling and BSIM3 User's guide, Kluwer Academic Publisher, 1999
  • Jan M. Rabey, Anantha Chandrakasan and Borivoje Nikolic, Digital Integrated Circuits, A design perspective, Prentice Hall, 2003
  • Naveed Sherwani, Algorithms for VLSI Physical Design Automation, Kluwer Academic Publisher, 2004